Semiconductor packaging is an integral component of modern electronics, as it facilitates and controls the flow of electricity, powering advanced technologies and devices that have transformed many aspects of modern life. The emergence and rapid acceleration of technologies that rely on power devices such as smartphones, laptops, EVs, photovoltaics, and AI has created strong demand for semiconductor packaging designs that can deliver power efficiently while mitigating the significant heat that is generated during electrical switching. A critical part of bringing a new packaging design to market involves validation of these enhancements. One way to validate packaging designs is through simulation.

This paper, published in the 2025 Conference of Science and Technology of Integrated Circuits (CSTIC), introduces a streamlined process using ANSYS Workbench, a simulation integration platform, for validating metal–oxide–semiconductor field-effect transistor (MOFSET) packaging. A MOFSET is a type of transistor that uses an electric field to control the current through a semiconductor. 

Simulation methods offer a powerful way to identify and optimize weak points through precise multi-physics coupling – a way to look at the impact of more than one type of physics. In the case of semiconductors, there are electrical, thermal and mechanical elements at play. 

According to the paper’s authors, early electro-thermal-mechanical simulations focused on metal–oxide–semiconductor (MOS) devices with voltage-driven circuit responses. Later, wide band gap (WBG) semiconductors became critical and prompted studies with electro-thermal-mechanical simulations on themselves. Research on packaging for insulated-gate bipolar transistors (IGBTs), an electrical semiconductor device that functions as a switch, using Simulink -COMSOL, PSpice-COMSOL or ANSYS for coupled simulations, has been reported. However, these studies often involve complex inter-software data transfers and lack board-level current-loading simulations.  

Board-level current loading refers to the amount of electrical current that flows from the power supply to the components and subcircuits on a printed circuit board (PCB). It is essentially the current drawn by the entire board to operate properly. The PCB serves as the backbone of the device’s circuitry.

The Process

The process presented in this paper demonstrates board-level electro-thermal-mechanical simulations and addresses wiring impact on temperature, internal thermal characteristics, weak points, and stress under power cycling. ANSYS Workbench is well-suited for this validation method as it provides a user-friendly interface, manages data, and integrates multiple analyses within a single environment, simplifying complex simulation workflows. 

A MOFSET is most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. MOSFET packaging designs focus on optimizing electrical and thermal performance while minimizing size. The ability to validate MOFSET packaging designs is important in the development of new power semiconductor devices at operational currents. 

A total of four PCB-package combined models were selected for simulations. The variables related to connection methods (clip and aluminum wire) and PCB layouts (plate copper layout and minimal trace layout).

Two MOFSET chip connection methods were tested: clip design and aluminum wire design

 

Two PCB layouts were tested: a copper plate layout and a minimal trace layout.

 

Matrix of the four PCB package combined models tested in this validation simulation.

 

Results

Temperature/Thermal Performance

Heat dissipation is crucial for MOSFET performance and reliability. Packages are designed with features like exposed pads, thermal vias, and internal heat paths to manage heat. 

Electro-thermal simulations revealed significant differences in temperature distribution based on PCB copper layout. For plate-style PCB designs (Models I and II), the highest temperatures occurred within the package, on the clip or aluminum wire bond. In minimal trace designs (Models III and IV), hotspots shifted to the copper traces on the PCB, with trace temperatures reaching 500-600°C due to excessive Joule heat. 

These results highlight the importance of robust PCB trace design to prevent extreme overheating and ensure the reliability of high-power applications.

Current Density and Joule Heat Distribution

The aluminum wire bond design exhibited higher current density, with hotspots at the chip's source connection and aluminum layer corners, while the clip design's highest density was at the package leads. Current density near the gate region was also higher in the aluminum wire design, making it more prone to localized high-density regions. These findings emphasize the impact of connection methods on reliability, as excessive current density can accelerate electromigration and increase failure risks. The aluminum wire design displayed enhanced density areas that led to localized hotspots on the chip surface.

Temperature Distribution

The simulation revealed clear differences between clip and aluminum wire designs. The highest temperatures occured on the clip or aluminum wire, not the chip. The clip design had a smoother heat distribution gradient (90°C–99°C), while the aluminum wire design exhibited a steeper heat distribution gradient (130°C–183°C), which increases the risk of wire bond lift-off due to surface detachment. These findings underscore the critical role of Joule heat in aluminum wire failure, often overlooked in previous analyses, especially for devices like IGBTs. 

These results emphasize the need to consider Joule heat effects in aluminum wire-bonded packages, particularly under high currents. The clip design, with its uniform thermal profile, offers better thermal reliability.

Stress

The solder's equivalent stress and strain were analyzed. The clip design revealed a minor risk of solder cracking with strain measured at slightly above the cracking threshold. In contrast, the aluminum wire design had a lower measured strain, suggesting a safer solder interface under power cycling.

For the aluminum wire design, stress analysis showed the highest equivalent stress at the wire heel, a common failure point for wire bonds. The measured stress indicated a high risk of lift-off failure.

Conclusion

In summary, this paper’s simulations identified potential weak points in internal and chip surface temperature distributions. Stress validation under power cycling conditions identifies failure risks in the chip, solder, and aluminum wires. The findings indicate critical areas for improvement in packaging design to ensure reliability under operational currents.

This proposed validation process of MOFSETs yields valuable data for future use. By understanding the different MOSFET packaging options and their characteristics, designers can select the best package for their specific application, optimizing performance, size, and cost. 

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